In contrast to conventional planar metal-oxide-semiconductor field-effect-transistors (“MOSFETs”), multi-gate transistors incorporate two or more gates into a single device. Relative to single gate transistors, multi-gate transistors reduce off-state current leakage, increase on-state current flow, and reduce overall power consumption. Multi-gate devices having non-planar topographies also tend to be more compact than conventional planar transistors and consequently permit higher device densities to be achieved. One known type of multi-gate, non-planar transistor, commonly referred to as a “FinFET,” includes one or more parallel fin structures (the “fins”) formed on a substrate, such as a silicon-on-insulator substrate. The fins extend along a first axis between common source and drain electrodes. At least one conductive gate structure (the “gate”) is formed over the fins and extends along a second axis generally perpendicular to the first axis. More specifically, the gate extends across and over the fins such that an intermediate portion of the gate conformally overlays three surfaces of each fin (i.e., an upper surface, a first sidewall surface, and a second opposing sidewall surface of each fin).
It is generally advantageous to locally interconnect semiconductor devices, when possible, to minimize circuit dimensions and to reduce the complexity and possibly the number of back-end-of-the-line layers required to complete the desired integrated circuit. It has, however, proven difficult to design circuits incorporating FinFETs (or other multi-gate semiconductor devices, such as triFETs) having a desired degree of local interconnectivity while satisfying current scaling targets, which have been significantly reduced and continue to be reduced in accordance with industry demands. In the context of multi-gate devices and high density scaling targets, circuit rules tend to severely restrict or entirely eliminate local interconnect techniques conventionally utilized in conjunction with lower density MOSFET circuits. For example, polysilicon gate routing, active area routing, deposited metal routing, and similar conventional local interconnect techniques are each associated with various drawbacks that render such techniques unsuitable or undesirable for employment in high density circuits that include interconnected FinFETs or other multi-gate semiconductor devices.
In view of the above, there exists an ongoing need to provide embodiments of an integrated circuit including multiple multi-gate semiconductor devices locally interconnected in a manner that is compatible with small scale circuit rules. It would also be desirable to provide embodiments of a fabrication method suitable for producing such an integrated circuit. Other desirable features and characteristics of the present invention will become apparent from the subsequent detailed description and the appended Claims, taken in conjunction with the accompanying Drawings and the foregoing Technical Field and Background.